Simulating integrated circuits has proved to be a very useful process for finding circuit design problems before product release. In particular, known testing techniques have been directed to CPUs (central processing units) and associated buses. Typically, in testing VLSI (very large-scale integrated) circuits such as these, a large number of different test cases are processed in order to uncover problem states. An example of test cases may be found in U.S. Pat. No. 5,956,476 to Ransom et al., which is incorporated herein by reference. In previous approaches, a large number of cases might be randomly generated by specifying a weighted mix of transaction (e.g., read, write) types. For example, a mixture of 20% reads and 80% writes might be generated. Using random generation, the timing relationship between any of the events is neither specified nor controllable.
FIG. 8 illustrates an exemplary topology utilized by known circuit simulation techniques. VLSI 801 is associated with two separate stimuli: internal BUS 802 and external bus 804 of BUS interface unit 803. It is appropriate to generate a number of test states associated with these two stimuli. Most pairs of stimuli do not lead to any problems. Accordingly, it is appropriate to isolate the problem states (i.e., pairs of stimuli) that give rise to circuit malfunction. In addition, it shall be appreciated that there is an additional degree of freedom associated with problem states. Specifically, problem states that are separated in time may nevertheless lead to problematic circuit behavior.
Test cases for application to such a system topology may be randomly generated. Random generation is illustrated in Cox, P., et al. “Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits”, IEEE Trans. Electron. Devices, vol. ED-32 No. 2, 471-478, 1985, which is incorporated herein by reference. Other examples of random generation of test cases include U.S. Pat. No. 6,018,623 to Chang et al., which is incorporated herein by reference.
Also, known techniques utilized to ascertain problem states include manual development of test cases. For example, a transaction might be set up on an external BUS at time t0 and then have a transaction injected onto the internal BUS at a time t=t0−tA. Also, tA is initially set to equal t1 and successively varied until t equals time t0. Also, tA may be varied until it reaches −t1. The hypothesis is that if there is any important timing relationship between the two transactions, that relationship would be discovered by exhaustively iterating the relative times of the two transactions.
Random generation of test states is fairly automatic. However, the amount of computational effort necessary to cover desired events can be very large. Also, random generation is problematic in that it is often difficult to repeat problem states. For example, if something changes in the execution of the model of the circuit under test, a purely random string of transactions may not re-trigger that event. Alternatively, handwritten generation of test states may identify problem states more easily. However, handwritten generation of states requires extensive hand coding by someone who has extensive knowledge of the system under test. Specifically, this technique requires significant input from highly skilled personnel.